1. Field of the Invention
The present invention relates generally to zero power non-volatile CMOS memory cells used with high density programmable logic devices (PLDs). More particularly, the present invention relates to a method for preventing turn-on of both transistors in a CMOS memory cell causing a significant drain on power supply current (Icc).
2. Background
FIG. 1 shows a conventional CMOS EEPROM memory cell for PLD applications. The memory cell 100 includes a PMOS transistor 102 and an NMOS transistor 104 with a common floating gate. Drains of transistors 102 and 104 are connected together to form the output of the CMOS cell 100. Capacitors 106 and 108 are connected to couple voltage to the common floating gate. Bias voltage is provided to the source of PMOS transistor 102 from a chip Vcc pin. Bias voltage is provided to the source of the NMOS transistor 104 through a chip ground or Vss pin. Control capacitor 106 supplies voltage from an array control gate (ACG) node. An NMOS pass transistor 110 supplies a word control (WC) voltage to tunneling capacitor 108 as controlled by a word line (WL) voltage supplied to its gate. The CMOS memory cell 100 is disclosed in U.S. Pat. No. 5,272,368 entitled “Complementary Low Power Non-Volatile Reconfigurable EECELL,” and in U.S. Pat. No. 4,885,719 entitled “Improved Logic Cell Array Using CMOS E2PROM Cells.”
Typical voltages applied for program, erase and read of the CMOS memory cell 100 are listed in Table I below. Programming indicates electrons are removed from the common floating gate, while erase indicates that electrons are added to the common floating gate.
TABLE IWCWLACGVccVssProgram1213.8000Erase0513.81212Read2.552.550The program, erase and read voltages of Table I are for transistors having a Vcc of approximately 5 volts during read operations. For lower voltage transistors operating with a lower Vcc, such as 1.8 volts, the voltages shown in Table I may be significantly reduced.
FIG. 2A shows a layout for the CMOS cell 100 of FIG. 1, while FIGS. 2B-2E show respective cross sectional views at BB′, CC′, DD′ and EE′ in FIG. 2A. The layout for the CMOS cell shown in FIGS. 2A-2E is formed in a p type substrate.
As shown in FIGS. 2A and 2B, control capacitor 106 includes n+ type implant regions 202 and 203 formed in the p type substrate. Overlying the n+ type implant regions 202 and 203 is a gate oxide layer (GOX) region 204. Provided above the gate oxide layer 204 is the common floating gate (F.G.) 206 .
As shown in FIGS. 2A and 2C, the tunneling capacitor 108 includes n+ implant regions 208 and 209 formed in the p type substrate. Overlying the n+ type implant regions 208 and 209 is a gate oxide 210 which includes a standard thickness portion 211 and a thinner tunneling portion 212. Overlying the gate oxide 210 is the common floating gate 206. The tunneling portion 212 of the gate oxide 210 provides a region to enable electrons to be applied to the floating gate 206 during erase and removed during programming.
As further shown in FIGS. 2A and 2C, the pass transistor 110 is formed by a polysilicon (POLY) word line (WL) region 216 on the substrate with a portion of region 216 overlying a drain n+ implant region 209 and another portion overlying a source n+ implant region 218.
As shown in FIGS. 2A and 2D, the NMOS transistor 104 includes source and drain n+ implant regions 220 and 222 in the p substrate. A gate oxide region 224 is placed on the substrate bridging regions 222 and 220. The common floating gate 206 overlies the gate oxide region 224.
As shown in FIGS. 2A and 2E, the PMOS transistor 102 includes p type source and drain regions 230 and 232 included in a n+ type well 236 which is included in the p type substrate. A gate oxide region 238 is placed on the substrate bridging the regions 230 and 232. The common floating gate 206 overlies the gate oxide region 238.
The CMOS memory cell 100 is advantageous because it enables zero power operation, zero power operation indicating that a component does not continually draw power when the component is not changing states. For instance, with an appropriate voltage applied to the common floating gate 206, PMOS transistor 102 will conduct and NMOS transistor 104 will not conduct. Current will then be provided from Vcc through PMOS transistor 102 to the output until the output is charged up to Vcc. In this configuration, no current will be provided through NMOS transistor 104 to Vss. Further, with another voltage stored on the common floating gate 206, NMOS transistor 104 will conduct while PMOS transistor 102 does not. The output will then discharge to Vss. No additional current will be provided through PMOS transistor 102 from Vcc to Vss.
To assure transistors 102 and 104 operate like a typical inverter, however, transistors 102 and 104 have threshold voltages set such that the CMOS inverter formed by transistors 102 and 104 in FIG. 1 will “switch” output states with transistors 102 and 104 transitioning together between OFF and ON states when charge is added to the floating gate or removed from the floating gate. In such a manufacturing process, the PMOS transistor 102 will have a threshold overlapping with a threshold of the NMOS transistor 104.
The transfer characteristics of CMOS transistors 102 and 104 manufactured in such a manner are shown in FIGS. 3A and 3B. As shown in FIG. 3A, PMOS transistor 102 remains ON for a floating gate to source voltage (Vfg) within a set range, driving the OUTPUT voltage VOUT to Vcc. And then, the PMOS transistor 102 will transition to OFF while the NMOS transistor 104 transitions to ON when the floating gate to source voltage increases further driving VOUT to Vss. FIG. 3B illustrates a region Vfgl where both the PMOS transistor 102 and the NMOS transistor 104 are on together.
The fault with the CMOS memory cell design shown in FIG. 1 with cells configured to “switch” occurs when the memory cell has an initial charge on the control capacitor 106 such that the floating gate is biased to the value Vfgl. At this bias voltage, 102 and 104 will both be ON or in a conducting state so a large Icc current can flow from Vcc to Vss through the transistors 102 and 104.
The first time the CMOS memory cell 100 is powered up, the charge on the floating gate 206 is unknown as it will be the residual amount of charge on the floating gate 206 after wafer fab processing. As a result, it is possible for the floating gate to be initially biased such that both transistors 102 and 104 are ON. If both transistors are ON, it may prevent the part from powering up properly as the memory array may contain multiple devices, creating a short circuit between Vcc and Vss capable of sourcing substantial current Icc and effectively shorting out the power supply to the chip.
A number of methods have been contemplated for preventing a substantial Icc from being drawn and affecting power-up of the chip. A first method is to provide additional current regulation circuitry in the power supply to limit the amount of current Icc provided to the memory array. A second method is to supply power to the memory array from a power supply separate from a power supply for the remaining chip circuitry. The separate power supply for the memory may then be shorted without preventing the overall part from powering up properly. A combination of the first and second methods have also been contemplated.